The creation of complex integrated circuits and semiconductor devices can be an expensive undertaking because of the large number of hours of sophisticated engineering talent involved in designing such devices. Additionally, integrated circuits can include read only memories and/or EEPROMs into which software, in the form of firmware, is encoded. Further, integrated circuits are often used in applications involving the encryption of information. In order to keep the encrypted information confidential, devices should be protected from being reverse engineered. Thus, there can be a variety of reasons for protecting integrated circuits and other semiconductor devices from being reversed engineered.
In order to keep the reverse engineer at bay, different techniques are known in the art to make integrated circuits more difficult to reverse engineer. One technique is to make the connections between transistors difficult to determine forcing the reverse engineer to perform a careful analysis of each transistor (in particular, each CMOS transistor pair for CMOS devices), and thwarting attempts to use automatic circuit and pattern recognition techniques in order to reverse engineer an integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to analyze each transistor carefully in a device can effectively frustrate the reverse engineer's ability to reverse engineer the device successfully.
A conductive layer, such as silicide, is often used during the manufacture of semiconductor devices. In modern CMOS processing, especially with a minimum feature size below 0.5 μm, a silicide layer is utilized to improve the conductivity of gate, source and drain contacts. In accordance with typical design rules, any active region resulting in a source/drain region is often silicided.
One reverse engineering technique involves de-layering the completed IC by means of chemical mechanical polishing (CMP) or other etching processes. The etching processes may, under some conditions, reveal the regions between where the silicide was formed on the substrate, and where it was not, i.e. the regions defined by the silicide block mask step and by regions where structures, such as a polysilicon gate, prevent the silicide layer from being deposited on the substrate. These regions may be revealed because, under some kinds of etches, there is an observable difference in topology due to different etching rates for silicided versus non-silicided silicon. The reverse engineer, by noting the silicided areas versus non-silicided areas, may make assumptions as to the function of the device. This information can then be stored into a database for automatic classification of other similar devices.
Some methods of protecting against reverse engineering may be susceptible to discovery under some reverse engineering techniques, such as chemical-mechanical polishing (CMP) or other etching techniques. For example, FIG. 1a depicts a possible top-down view of a false transistor FT made in accordance with U.S. patent application Ser. No. 09/758,792 after etching. During the manufacturing of the false transistor, and in accordance with normal design rules, the silicide block mask allows for a silicide layer 15, see FIG. 1b, to be placed completely over the active regions 12, 16 in substrate 22, and optionally over gate layer 14. Gate layer 14 may be a polysilicon layer. During the CMP reverse engineering process, the gate layer 14 would be removed, thereby resulting in the top-down view as shown in FIG. 1a. As shown, the silicide layer edge 18 aligns with the gate edge 11, 13, thus the reverse engineer only sees one line along the gate edge 11, 13.
The top-down view of the false transistor is different from a top-down view of a true transistor and as such, the difference may be a signature that the transistor is not a true transistor.
For functional or true transistors, as shown in FIGS. 2a and 2b, the silicide layer edge 18′ is offset from the polysilicon gate layer 14 due to the presence of sidewall spacers 19 that are formed adjacent to gate layer 14. A lightly doped density (LDD) implant 10 is typically formed after the formation of the gate layer 14 and before the formation of the sidewall spacers. After sidewall spacers 19 are formed, active areas 12, 16 are typically formed in the substrate. The formation of active areas 12, 16 saturate most of the LDD implant, so that only the portion of the LDD implant 10 that is under the sidewall spacers 19 effectively remains. A conductive layer, such as silicide 15, is typically placed over the active areas 12, 16 and over the gate layer 14. The sidewall spacers 19 prevent the silicide from being deposited upon the exposed substrate in those areas. Thus, the artifact edge 18′ is spaced from and lies mostly parallel with the edges 11, 13 of the gate layer 14 for a true transistor TT. Thus, from the examination of the top-down views of FIGS. 1a and 2a the reverse engineer may be able to determine that a structure originally placed in the area was in fact a (i) false transistor FT meant to confuse the reverse engineer due to the absence of artifact edges 18′ lying spaced from and mostly parallel with edges 11, 13 of the polysilicon gate 14 or (ii) a true transistor TT. A reverse engineer could then program computer software to recognize the absence of artifact edges 18′ of the silicide layers lying separate from and being mostly parallel with the edges 11, 13 of the gate layer 14 as indications of false transistors FT among a plurality of true transistors TT formed on a single integrated circuit device or chip.
It should be understood that although FIG. 1b depicts active regions 12, 16 adjacent to the gate layer 14 and FIG. 2b depicts LDD implants 10 adjacent to the gate layer 14, it is extremely difficult, if not impossible, for the reverse engineer to determine a difference in both doping levels and doping types (n or p) between the LDD implant 10 and the active regions 12, 16.
Our U.S. patent application Ser. No. 10/637,848 teaches a semiconductor device and a method of manufacturing semiconductor devices that uses artifact edges to confuse the reverse engineer. Providing artifact edges that are not indicative of the actual device formed will further confuse the reverse engineer and result in incorrect conclusions as to the actual composition, and thus function, of the device.
We have further developed the teachings about in order to allow LDD implants and, preferably in combination with judicious patterning of silicide layers, to interconnect (or not interconnect) active regions of different transistors in a way which is very apt to confuse the reverse engineer. This new technique can be used with the techniques disclosed in the related application to further confuse the reverse engineer.